How to use "wait for 20 ns" in VHDL testbench? (Quartus)

[childs]

Quartus is complaining on non-synthesizable "wait for 20 ns" in testbench. But it IS a TESTBENCH. I was trying to use the wait-statement to create clock, so I don't think I can use clock edge to replace the time.

This is my first time trying to write testbench without any input/output ports. Not even clock. Is there any setting that I need in order to compile this non-synthesizable testbench? Did I miss anything? Also, did I misspell "synthesizable"?...

Thanks in advance

 

[TrickyDicky]

You cant compile testbenches in Quartus. You need to use a simulator like modelsim!

 

[shaiko]

you spelled it correctly.

please post your testbench code. just to see if everything is correct.
I don't think that Quartus supports testbenches.

Bare in mind, that the simulation capabilities of Quartus / ISE are limited.
Generaly, the use of synthesis tools for simulation is discouraged. I suggest you work with a designated simulator (such as ModelSim or Active HDL) while being assisted by the synthesizers RTL viewer to get the idea of how your code is translated into logic.

 

[mrflibble]

Bare in mind, that the simulation capabilities of Quartus / ISE are limited.
Generaly, the use of synthesis tools for simulation is discouraged. I suggest you work with a designated simulator (such as ModelSim or Active HDL) while being assisted by the synthesizers RTL viewer to get the idea of how your code is translated into logic.

Please excuse the semi-hijack... You discourage the use of for example xilinx ISim. I can imagine that modelsim is better, but what practical cases did you run into ISim being sucky and modelsim rescueing the day? Reason I ask is because I regularly use ISIm, and would appreciate any pointers what to watch out for...

And on topic: You cannot synthesize delays like that. If you want delays in actual hardware then you'll have to use a counter or FSM etc.

Edit: sorry, misunderstood the OP. After rereading I see that you are only trying to simulate it, and it whines about it not being synthesizable.

See this VHDL example for clock generation: VHDL tutorial - part 2 - Testbench

 

[shaiko]

mrflibble,

I don't discourage the use of ISim - What I said is that the use of FPGA vendor tools for simulation is being generally discouraged.
I'm sure that ISim and Quartus have there place - maybe for simpler designs.

Altera itself advocates the use of ModelSim even though it spent good time and money designing its own simulator.
I've heard that ISim doesn't have full support for VHDL 2008 and No system verilog support.

 

[TrickyDicky]

Altera have stopped developing their simulator. It is not available from Q9+
Xilinx are working to make their simulator work better (but it doesnt work as well as modelsim. It has poor support on some of the lesser used parts of VHDL eg protected types - But I keep finding bugs for those in modelsim too and 2008 support doesnt exist yet)

---------- Post added at 23:12 ---------- Previous post was at 23:12 ----------

Altera have stopped developing their simulator. It is not available from Q9+
Xilinx are working to make their simulator work better (but it doesnt work as well as modelsim. It has poor support on some of the lesser used parts of VHDL eg protected types - But I keep finding bugs for those in modelsim too and 2008 support doesnt exist yet)

 

[mrflibble]

I don't discourage the use of ISim - What I said is that the use of FPGA vendor tools for simulation is being generally discouraged.
I'm sure that ISim and Quartus have there place - maybe for simpler designs.

Understood. I got it that you were talking in general. I dragged ISim into it as a specific example, since I use that specific simulator. Didn't mean to imply that you were implying anything.
As for simpler designs ... that is probably why personally I haven't run into anything problematic with isim. I don't do this for work, I'd consider myself more of a serious hobbyist in the verilog department. And as such my projects are not enterprise scale huge, so maybe that's why isim is okay so far.

Altera itself advocates the use of ModelSim even though it spent good time and money designing its own simulator.
I've heard that ISim doesn't have full support for VHDL 2008 and No system verilog support.

Good to know. And I can confirm isim does not support systemverilog as of version 13.3. The latest *cough* "roadmap" *cough* I read was "yes yes we (xilinx) will support systemverilog in ISE version 14 somewhere in 2012". Suuure, I'll believe that when I see it, given the track record so far. But we can always hope.

---------- Post added at 22:36 ---------- Previous post was at 22:25 ----------

Altera have stopped developing their simulator. It is not available from Q9+
Xilinx are working to make their simulator work better (but it doesnt work as well as modelsim. It has poor support on some of the lesser used parts of VHDL eg protected types - But I keep finding bugs for those in modelsim too and 2008 support doesnt exist yet)

Thanks for the clarification. Reading your + shaiko's response it seems VHDL 2008 is still problematic. Which somewhat validates my decision to resist the diabolical urge. What urge is that you ask? Well, after being fed up with verilog's lack of <fill_in_handy_feature_here> for the Nth time, I can't help but wonder how life is in VHDL country. At times I've seriously considered ditching verilog and try vhdl. And/or ditching xilinx + concentrating on Altera, since I can't do everything. But then it's probably a "the grass is greener in other pastures of which you don't know the minefield yet" thing. VHDL in practice (meaning using vhdl with real available tools as opposed to how cool things look on paper) no doubt has it's problems, so I would just be trading problem #1 for problem #2.

So far the first little tests with systemverilog are positive, so I can only hope for better vendor support ASAP. synplify + par + map + modelsim seems to do the trick so far. ISE editor is total crap with systemverilog but oh well.

(and again sorry for the now not-so-semi thread hijack

 

[shaiko]

Generally speaking, Quartus and ISE are decent synthesis tools...but sim wise - they're considered inferior to the big players from Mentor and Synopsys.

I hope Altera and Xilinx focus their resources on making better PLDs instead of competing on that extra buck from selling CAD software.
Take a look at Actel - being a much smaller company then Xilinx and Altera, they make very few software tools. Yet, they have a very interesting product portfolio...

 

[TrickyDicky]

For altera, you cant get better than Quartus for Synthesis for altera - Synopsis will admit as much. Altera do a lot of work on their tools and they are pretty good. Afaik, there are no synthesis tools that fully support VHDL 2008 yet (altera support a few handy bits, afaik Xilinx dont support any). Xilinx have always focussed more on products rather than their tools, hence why their own tools have always had a pretty poor reputation, while altera have always worked hard and not really allowed other companies to write synthesis software. Synopsys are just started to support VHDL 2008.

MrFlibble. Ive never given Verilog a go. But Everything I read makes me think Ill just get pissed off with vanila Verilog. But I hear SystemVerilog is where it's at in terms of Verification. But VHDL has done fine for me so far (bitmap reading/writing, random stimulus generation, behavioural models - one of which included a lot of linked lists!).

 

[shaiko]

TrickyDicky,

Have you ever designed ASIC (front end)?
If so, did you use VHDL ?

 

[mrflibble]

Generally speaking, Quartus and ISE are decent synthesis tools...but sim wise - they're considered inferior to the big players from Mentor and Synopsys.

Regarding the "decent synthesis tools", ISE (XST) is indeed decent, but no more than that IMO. No doubt my ignorance plays a part here, but sometimes even for a fairly trivial bit of verilog it thinks of the most stupid stuff. It could very well be that this is because I don't know how to get XST to generate the proper hints for the place & route, but despite reading quite a bit about it I can't say it's very intuitive. If I want stuff to go fast (in the 400-500 MHz range on spartan-6) I have to do a lot of hand holding (read: RLOC the crap out of it). That being said, for say ~ 200 MHz no such problems, so maybe I'm just too picky.

And regarding simulation, I'll readily believe modelsim is superior. Although my projects are small enough that I don't really run into real issues here. The only thing so far is a timing related project that is heaviliy into asynchronous fpga abuse, and as such I needed to do a lot of post place & route simulation just to verify the functionality of the design. Yeah, I know, shame on me. That resulted in me having to wait for an hour+ on a then quite decent Q9550, after just one small code change. So that gave me a great excuse to upgrade to a sandybridge system.

I hope Altera and Xilinx focus their resources on making better PLDs instead of competing on that extra buck from selling CAD software.
Take a look at Actel - being a much smaller company then Xilinx and Altera, they make very few software tools. Yet, they have a very interesting product portfolio...

I suppose that is a matter of perspective. When you work for a big company that has several seats of all the great tools I can understand this. However when your tool budget is limited then it's nice if there's an affordable all-in-one solution. Then again, the big spenders are the big companies, so no doubt that perspective will win.

---------- Post added at 01:22 ---------- Previous post was at 01:10 ----------

For altera, you cant get better than Quartus for Synthesis for altera - Synopsis will admit as much. Altera do a lot of work on their tools and they are pretty good. Afaik, there are no synthesis tools that fully support VHDL 2008 yet (altera support a few handy bits, afaik Xilinx dont support any). Xilinx have always focussed more on products rather than their tools, hence why their own tools have always had a pretty poor reputation, while altera have always worked hard and not really allowed other companies to write synthesis software. Synopsys are just started to support VHDL 2008.

Quartus for VHDL synthesis being quite good is indeed what I hear from several people. And xilinx being less so is also what I hear from several people (myself included when I resort to talking to myself ).

MrFlibble. Ive never given Verilog a go. But Everything I read makes me think Ill just get pissed off with vanila Verilog. But I hear SystemVerilog is where it's at in terms of Verification. But VHDL has done fine for me so far (bitmap reading/writing, random stimulus generation, behavioural models - one of which included a lot of linked lists!).

No doubt you will just get pissed off by vanilla verilog. I get pissed off by vanilla verilog on a regular basis! That's why sometimes it has me seriously contemplating vhdl. It's also why I'm now playing around with systemverilog, and I must say so far it's a breath of fresh air. Actual decent interface definitions for modules without having to write 2435987345 port definitions for every submodule. For verification I don't have much experience yet with systemverilog, but I did read a lot of positive things about it. I do know that I find plain vanilla verilog lacking in that respect. I found that with a lot of perl post processing I can get the job done, but hopefully I can do all that now in systemverilog without needing extra scripts just to compensate for crippled language/tools.

 

[childs]

Well... I wasn't sure how this thread turns out to be synthesizer & simulator discussion, haha, but it is really interesting.
I will start to look at modelsim now. Thanks guys!

 

[shaiko]

you can download modesim student edition.
I suggest you download it directly from Mentor (student edition).

 

[gck]

Hi Childs,

when you add the testbench in ISE project, a window pops out asking for the association. select the simulation option.
This will help the compiler to overlook the non-synthesizable constructs used in testbench.

This works for me.

GCK