sea_mist
Newbie level 4
Hello,
I have made my system needed memory in memory compiler, then I used component & port map in my .vhd file to use the memory.
But there is are some problems which I can not solve.
1- In MC output file some libraries are included :
use WORK.vlibs.all;
use WORK.lib_cells_pkgs.all;
but when I run modelsim to generate the saif file, it does not know these two libraries and give error.
2- It does not know some Identifier which are used in MC out put, like cat in "constant ClkPort : string:=cat("CLK",PortName);"
from where I should bring the WORK.lib_cells_pkgs.all ?
I can not use MC out put in DC.
please help me ....
I have made my system needed memory in memory compiler, then I used component & port map in my .vhd file to use the memory.
But there is are some problems which I can not solve.
1- In MC output file some libraries are included :
use WORK.vlibs.all;
use WORK.lib_cells_pkgs.all;
but when I run modelsim to generate the saif file, it does not know these two libraries and give error.
2- It does not know some Identifier which are used in MC out put, like cat in "constant ClkPort : string:=cat("CLK",PortName);"
from where I should bring the WORK.lib_cells_pkgs.all ?
I can not use MC out put in DC.
please help me ....