How to use block RAM in Spartan-3E?

[childs]

spartan 3e block ram

Referring to above question... May i know how to use block RAM in Spartan-3E?

Or any place i can find related information? (I cannot determine which keywords or which parts i shall search, googling and searching in Xilinx webpage, most of the searched results mentioned about the problem faced instead of how to use it ..... )

 

[pwq1999]

spartan 3 block ram

see the Logicore in ISE, maybe you will find it.

 

[saikat]

ramb16_s18_s18

Make sure that you have used a synchronous reset in the RAM block. Xilinx ISE will automatically infer the ARRAYS (in your code) you may have used for data storage purpose, mapped into block RAM available in the device. Default "MAP" and "P and R" settings will do it. There is no need for any special settings.
You can find various kind of synchronous RAM i.e. single port, dual port etc. code template in Xilinx ISE code templates.

 

[echo47]

using rams blocks spartan 3

ISE provides several ways of putting a Block RAM into a Xilinx FPGA.

You can infer the RAM with HDL code by using a large register array. Be sure to write your HDL in the recommended way. If you are using ISE's XST synthesis tool, see the ISE "XST User Guide" chapter "HDL Coding Techniques".

You can instantiate the block RAM primitive directly into your HDL. See the ISE "Library Guide" for your particular FPGA type, and then look for design elements having names such as RAMB16_S18_S18. This is a reliable technique but it is somewhat tedious because there are many ports to connect.

You can use ISE's CORE Generator (coregen) to build a memory module to your specifications. After you launch coregen, look for the "Memories & Storage Elements" section, and click something under "RAMs and ROMs". Then you can read the core's data sheet to see if it's appropriate for you needs.

 

[naz56]

spartan 3e

r u sure arrays in a verilog code are put into Block RAM by default???