How to synchronise an asynchronous input so that I can avoid metastability?

[xstal]

Hi,

I want to know how can we synchronise an asynchronous input so that I can avoid metastability?

One solution is to add two flops in series (synchroniser) at the asynchronous input. But this will work only if the metastability period of the flop is less than the clock period + setup time of the next flop. i.e. the flop comes out of the metastability well before the timing window of the next flop.

My doubt is that if the metastability period is more than or equal to one clock period, then how we will avoid metastability??? Is there any solution??????

 

[banjo]

Metastability

The only way to deal with a truely async input is to run it through a flop chain to sychronize it.

If the async input has an unknown phase to the internal clock, but you are sure that this phase will be constant for some interval, you can use the dual flop approach. Form two chains of sychronizers, one using rising edge flops and one using falling edge flops. (Then pick the one with the best output. Once you are in the other clock domain, you can easily move from the falling edge clock back to the rising edge. ) Everytime an event happens like a power cycle, you will need to again do the syncronizer selection process over again.

Most FPGAs are metastability hardened. They do not go into long term metastabile states. Look at the apps notes for the logic family you are using, this is probably discussed. Therefore the flop chain works because if you miss the setup time for the first clock, you will more than make it for the next clock. This assumes that the two clock rates are equal or that you are transitioning from a slower external clock to a faster internal clock.

If the external clock is faster than the internal clock, then you have a problem! The only good solution to this is a dual port FIFO. Since the external clock is faster, the data can only be arriving in bursts or your FIFO will quickly overflow.

 

[GoodMan]

Re: Metastability

where can find any doc for it ?

 

[banjo]

Metastability

I would guess typing the FPGA or CPLD vendors name and the word metastability into a search engine. When I googled "Xilinx metastability", I got lots of hits. For example,

https://www.xilinx.com/bvdocs/appnotes/xapp094.pdf

 

[xstal]

Re: Metastability

Thanks Banjo for replying and putting things together. However my question is still not replied.
Thanks

 

[banjo]

Metastability

I guess we are not understanding your real question then. If you have a truely async event, it must last longer than one period of your capture clock. Otherwise, the signal is never active during a clock edge and you miss the pulse entirely.

So, having set the lower pulse width of the async event to clock_period+, meaning clock period plus a little bit, there are two possible pulse widths within the part. First you can get a pulse 1 clock wide, or due to either meta events or location of the async event a pulse 2 clocks wide. This time distortion is an artifact of sampling an async event and there is nothing you can do about it.
The above comments hold in general for sampling clocks frequencies under 200MHZ in most FPGAs assuming that you also double buffer the input as previously described. Above 200MHZ there is a small chance, that it may time distort to an extra clock cycle or two. This is because if you transition the async event at just the right point you can lock up the flop for a short period of time.

The above was assuming that the async pulse is normally a zero and pulses to one momentarily. If it is normally a one then the same thing occurs only the logic levels are reversed.

True metastability events are rare in modern FPGAs and logic. In my experience, unexplained events that people initially blamed on metastability have in every case later been shown to be logic errors or software errors. Look at the numbers FPGA docs, the probablities they quote are very very low.

 

[GoodMan]

Re: Metastability

Thanks Banjo for your help !