How to SPICE simulatation after Place and Route.

[gezzas525]

Carrying on with the UMC libraries ive gotten the hang of buildgates and silicon ensemble and also creating .sdf for simulation in modelsim. Now I want to check my designs in spice after P&R, I was told the problem is that we dont have the spice information (only the basic design kit) for the standard cell libraries hence we cannot do even a power analysis. What is the procedure to simulate P&R circuits?

 

[hqqh]

Hi,

after the place&route you have gdsII data of your design, is this correct? If yes, you need to run a layout extraction tool (like diva, dracula or assura) to get a spice netlist for simulation. in such a extraction tool, all instances are defined by their geometrical properties in the layout. So the tool scans the gdsII data for this shapes and re-builds a flat netlist. in this netlist there are thousands of parasitc resistances and capacitances. i saw a tool in cadence dfII (ConcICe) that can reduce the number of devices by concentrating devices --> a netlist with a reduced number of devices.

Greetings,
hqqh