umairsiddiqui
Full Member level 2
Hi,
I'm trying to implement *data recovery* from an incoming serial data stream. The scheme is
based on Xilinx xapp224. Issue is now it has to be implemented in ASIC (90ns). Fortunately
the solution doesn't require any FPGA specific technique.
However it is required to put a systhesis constraint:
First see the Screenshot.png
the requirement is that incoming data (DATAIN) is applied to four flip-flops, two clocked by CLK (one rising edge and one falling edge) and two by CLK90 (rising and falling edges). It is important
that the delay from the input pin to these four flip-flops be almost equal. The absolute delay is irrelevant; only the skew is important.
In Xilinx FPGA, This is easily achieved by giving the software a MAXSKEW parameter for this net, of 500 ps, for example.
net datain maxskew = 500 pS ;
How to perform this on Design Compiler?
regards
I'm trying to implement *data recovery* from an incoming serial data stream. The scheme is
based on Xilinx xapp224. Issue is now it has to be implemented in ASIC (90ns). Fortunately
the solution doesn't require any FPGA specific technique.
However it is required to put a systhesis constraint:
First see the Screenshot.png
the requirement is that incoming data (DATAIN) is applied to four flip-flops, two clocked by CLK (one rising edge and one falling edge) and two by CLK90 (rising and falling edges). It is important
that the delay from the input pin to these four flip-flops be almost equal. The absolute delay is irrelevant; only the skew is important.
In Xilinx FPGA, This is easily achieved by giving the software a MAXSKEW parameter for this net, of 500 ps, for example.
net datain maxskew = 500 pS ;
How to perform this on Design Compiler?
regards
