How to simulate SFDR of a 12-Bit DAC

[waosai]

dac sfdr

I want to test my DAC's SFDR spec in Hspice.
The spec. of the DAC is: 125-MHz/12-Bit
Someone tells me use the following relationship to setup my FFT analysis in hspice:
np*Tck=Tsig*N
where np is the sampling points with the value of 1024 usually; Tck=1/125MHz is the period of clock; Tsig is the period of sine wave; N the numbers of signal (N must be odd).
Then using FFT statement in hspice:

..................................
.param N=99
.param np=1024
.param fck=125E6
.param Tck=1/fck
.param starttime=100n
.param stoptime='starttime+np*Tck'
.fft v(out) np=1024 from=starttime to=stoptime
......................................

Anyone can tell me whether the above statement is right?
And another question. The scale of the circuit is very large. So it requires large time to complete the simulation for hspice(about two weeks on my pc, using hsim). Is there any method to solve this problem?

 

[chungming]

sfdr dac

I want to test my DAC's SFDR spec in Hspice.
The spec. of the DAC is: 125-MHz/12-Bit
Someone tells me use the following relationship to setup my FFT analysis in hspice:
np*Tck=Tsig*N
where np is the sampling points with the value of 1024 usually; Tck=1/125MHz is the period of clock; Tsig is the period of sine wave; N the numbers of signal (N must be odd).
Then using FFT statement in hspice:

..................................
.param N=99
.param np=1024
.param fck=125E6
.param Tck=1/fck
.param starttime=100n
.param stoptime='starttime+np*Tck'
.fft v(out) np=1024 from=starttime to=stoptime
......................................

Anyone can tell me whether the above statement is right?
And another question. The scale of the circuit is very large. So it requires large time to complete the simulation for hspice(about two weeks on my pc, using hsim). Is there any method to solve this problem?

First i am not fimiliar with DAC , i just a beginer of sigma delta ADC.
But I find your statement have a problem.......
N is not just an odd number , it must be a prime number like: 7, 11,13,17,19,23,29,31.........
N/np=Fin/(sampling freq)
And your spec is 12bit , your np may be too samll , may be np=4096 will have a better result, but longer simulation time............

 

[waosai]

sfdr simulation

That's a good advice. However I also have questions.
(1)What's the meaning of "better results" and how to determine the value of np?
(2)Why should N be a prime number? If Fin/(sampling freq)=4, np=4096, then N=1024? How is prime number got?

Thanks a lot!

 

[chungming]

sfdr hspice

sorry i am not english native
my english is not so good can explain it
the pdf is the reference of it
may be can help you

https://www.analog.com/UploadedFiles/Associated_Docs/495568568Section8.pdf

 

[waosai]

hspice dac sfdr

Anyway thanks a lot!

 

[lovseed]

dac fft

The basic idea to have np*Tck=Tsig*N lies in that when you have np samping points, the total time is np*Tck, and the signal will have experienced N complete cycles. It is very important to have integer data cycles, otherwise spectral leakage will occur in FFT analysis.

usually np should be power of 2 because of the FFT intrinsic characterics. To determine Tsig, you can use two method:
(1) nyquist frequency : when you saying that your DAC can work with 125M sampling, it means that for data frequency up to nyquist frequency rate, the DAC will still work properly. In reality, you can choose a data freq very close nyquist frequency(75.5MhZ). i.e you can choose 15/32 * 125M or 31/64*125M
(because np is power of 2, you can see why we use 32, 64 ...)
(2) just set data freq to 1M-10M as your application cares. you DAC will surely show better performance than (1).

As for np, 512 point is enough, otherwise the simualtion time is un-endurablely long, and you have no other method to speed up the post-layout simulation with enough accuracy.

you'd better pick out the discrete stable sampling points(not with those points still in oscillating) from your post-layout simulation and use this data to run discrete FFT with matlab. This gives the true SFDR,SNDR when DAC settles down.
Direct FFT analysis in HSPICE surely will have a worse result, because the overshoots, noise, oscillation are all contained in the transient result.

Finally you need to make sure your input digital code is right at the beginning of your simulation. This digital code usually is generated by a script asuming a fsig data sampled and converted by an ideal ADC and the output of the ADC is the digital code to be feed to DAC.

 

[gdhp]

simulating sfdr

hi waosai
for simulate SFDR in hsice, how can i generate a digital sin wave? Can you tell me the detail?
Thank you!

 

[Vamsi Mocherla]

how to measure period of a wave in hspice

Hey very importantly for a DAC, you should make sure that the width of sampling period should match the settling of your sampled output. That means you have to take atleast a point after every settled sample of the DAC. This period is very critical to give the right SFDRs.

If you are using HSPICE, only punch values at the end of each sampling period @ 125 MHz. These values shall be subjected to FFT then. Or else, the measured values will give rise to distortion components.

Digital Sinewave can be generated using MATLAB or Verilog A models. If you have access to Cadence environment, use Verilog A model for 12 bit ADC @ 125 MHz to generate the digital sinewave. If you use MATLAB, then you have to convert the signals to analog PWL sources in SPICE. A program called BITGEN can be used for this. It should be freely available on the web

 

[paladinzlp]

sfdr simulation of dac

hai gdhp
You can design a ideal 12bit ADC using hspice and
input sin wave when you only hspice.
Of course , you can use verilog-A design model to design the ideal ADC when cadence environment.

 

[gdhp]

hspice dac sfdr fft

thank you paladinzlp
i know your mean

 

[gdhp]

what is sfdr and how is it measured

hi lovseed:
in you reply"you'd better pick out the discrete stable sampling points(not with those points still in oscillating) from your post-layout simulation and use this data to run discrete FFT with matlab. This gives the true SFDR,SNDR when DAC settles down.
Direct FFT analysis in HSPICE surely will have a worse result, because the overshoots, noise, oscillation are all contained in the transient result. "

i have some question about the fft simulation:
1) how can you verify the point you get in the fft is the settled points? Especially in MATLAB how to choose the point ?

 

[lovseed]

12-bit sinewave on matlab

hi lovseed:
in you reply"you'd better pick out the discrete stable sampling points(not with those points still in oscillating) from your post-layout simulation and use this data to run discrete FFT with matlab. This gives the true SFDR,SNDR when DAC settles down.
Direct FFT analysis in HSPICE surely will have a worse result, because the overshoots, noise, oscillation are all contained in the transient result. "

i have some question about the fft simulation:
1) how can you verify the point you get in the fft is the settled points? Especially in MATLAB how to choose the point ?

I think your design spec will specify the settling time of your DAC (say 15ns).
First make sure your design meet the spec, then you can measure the point 15ns after the ouput begin to transition.

Correction to my previous statement.
HSPICE fft analysis can also gain good result, if you specify the fft start time point , end time point, and np correctly. make sure the waveform duration you performed fft is of interger times of the data period.

 

[izengard]

Co simulation

hello,
i have trouble in dac simulation in @DS.
input is discrete time x[n], and output is analog x(t).
i make my sub_analog block and use it in dsp network when i run simulation (DF) and display result,it's include only discrete time and i lose data between two sample!
how i can run a transient simulation wen input is discrete time?
i want to use a sine wave between to sample to build a RF-DAC , when i lose data between to sample so sine wave does not effective !

 

[abab1394]

Please add option with fft_accurate to the Hspice ...