Laverne
Newbie level 5
modelsim vunit file
Hi all,
Can some please verify if this is true...
For simulation, instead of writing a regular testbench you would write a psl file for your design and use Modelsim to simulate.
I am very new to this vhdl stuff and have been doing lots of reading but still confuse
If it is true then please provide a simple design with psl so that I can follow through it.
Thanks in advance
regards
Hi all,
Can some please verify if this is true...
For simulation, instead of writing a regular testbench you would write a psl file for your design and use Modelsim to simulate.
I am very new to this vhdl stuff and have been doing lots of reading but still confuse
If it is true then please provide a simple design with psl so that I can follow through it.
Thanks in advance
regards