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I give the solution. I have already worked by this version.
If you want syntisis correctly you design you must give to synopsys a lib technolgi but you can work by synopsys lib. to do it folow this instruction:
- in link library click on brows then go to 'library' dir and open 'syn' directiry and choose thise file 'lsi_10k.db'
-same steps for traget library
-same steps for Symbole library but you choose lsi_10k.sdb
NB: you must erase 'your_library.db' from all and keep the '* ' on link library
there is one more step to do :
-display "command window" and you open your diroctory that contain your design (your verilog or vhdl file) exp "c:/my_design"
enjoy it!
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