vny
Newbie level 4
hello,
am doing my project in iverilog . i have reached a particular stage where i get a 17 bit out put from a 8 bit input(after multiplying and sign adjustments stages). now i want to revert back my 17 bit input to the first stage input register which is actually 8 bit. how can i round off 17 bit to 8 bits . there are some negative numbers also which is represented in 2's complement form.
please help as i am stuck with this and not able to proceed further
am doing my project in iverilog . i have reached a particular stage where i get a 17 bit out put from a 8 bit input(after multiplying and sign adjustments stages). now i want to revert back my 17 bit input to the first stage input register which is actually 8 bit. how can i round off 17 bit to 8 bits . there are some negative numbers also which is represented in 2's complement form.
please help as i am stuck with this and not able to proceed further