how to remove glitch in neural amplifier

[hamid123]

how i should design a reset pulse generator in a neural amplifier ?

i am designing a neural amplifier from a paper.it make the bits lower by lowering amplitude for optimization in a/d. i uploaded a picture that shows the general circuit .it has an ota and 2 comparator an or and reset pulse generation block . i know the internal circuit of all of the blocks unless the reset pulse generation block that i cant find out what is the internal circuit of that. can anyone help me ? the ieee link to the paper is below thanks .
https://ieeexplore.ieee.org/document/6709768/

 

[RobertFalbo]

Re: how i should design a reset pulse generator in a neural amplifier ?

Is it just a fixed frequency reset pulse?

 

[hamid123]

Re: how i should design a reset pulse generator in a neural amplifier ?

according to the paper input frequency is constant . when reset pulse generator is operating it makes the amplitude lower and the output voltage is folding.

 

[hamid123]

hi i'm designing a neural amplifier and i have got the required results but it has a 30 mv glitch i need to remove it with a simple circuit what should i do ? i attached the required schematic and an image of the output .thanks in advance.
output waveform :

tgate switch that has this glitch

general circuit

 

[FvM]

Merged the old previous posts into the thread because they explain the circuit purpose.

Presume some glitches are unavoidable by design. Did you review the IEEE article in this regard?