How to model a 3 input NAND gate in HSPICE?

[RDRyan]

In HSPICE manual, there is a example about "Modeling with Digital Behavioral Components". It use E and G element to model a NAND/AND gate. as below:

e nandout 0 nand(2) in1 0 in2 0
+0.0 5.0v
+0.5 4.8v
+1.0 4.5v
+4.0 0.5v
+4.5 0.2v
+5.0 0.0v

I don't know what is that "
+0.0 5.0v
+0.5 4.8v
+1.0 4.5v
+4.0 0.5v
+4.5 0.2v
+5.0 0.0v " mean? why does it use that?

and If I want to model a 3 input NAND gate, how should I do?

Thanks very much!

Ryan

 

[linuxwinner]

Re: what's that mean?

I think it is in-out voltage relationship in list form.

 

[renwl]

what's that mean?

I think it's similar to the truth table.

 

[chenjia]

what's that mean?

you should read nand(2),I think it will have the information you need

 

[hr_rezaee]

what's that mean?

Hi

"gatetype(k) May be AND, NAND, OR, or NOR. The value of k is the number of inputs of the gate. The x and y terms represent the piecewise linear variation of output as a function of input. In the multi-input gates only one input determines the state of the output.
"

http://www.ece.uci.edu/docs/hspice/hspice_2001_2-206.html

regards

 

[RDRyan]

what's that mean?

Thank you, hr_rezaee!

Thanks for all of you guys's comment.

I understand it now.