mo.khairy.mo
Member level 2
Hi all,
i'm writing a vhdl code of ALU on xilinx sparatn-6 XC6SLX45T i constrained the clock to be 2ns (500 MHZ) but when i synthesis the design using XST it's timing summary says that
when i implement the design the tool can't map the design due to the following error
could anyone please help me to fix this error
BTW i need to run the design on the minimum clock period as much as possible
thanks in advance
i'm writing a vhdl code of ALU on xilinx sparatn-6 XC6SLX45T i constrained the clock to be 2ns (500 MHZ) but when i synthesis the design using XST it's timing summary says that
Code:
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 11.784ns (Maximum Frequency: 84.859MHz)
Minimum input arrival time before clock: 6.314ns
Maximum output required time after clock: 3.703ns
Maximum combinational path delay: No path found
when i implement the design the tool can't map the design due to the following error
Code:
At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
(command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
could anyone please help me to fix this error
BTW i need to run the design on the minimum clock period as much as possible
thanks in advance