How to make use of deadzone in PLL?

[arsenal]

always heard that deadzone needs to be removed in pll, and some very experienced engineer told me that actually deadzone can be utilized somehow. Then when should we make use of it?

thanks,

 

[rhaynes]

By dead zone I assume you mean the issue with phase detectors and their operation near zero phase error. From a frequency synthesis view point the only thing I have done with the dead zone is to have an additional circuit monitor the position of the locked edge within the dead zone and apply a fine correction to the VCO. But that was just indirect way of removing the dead zone (as opposed to fixing the phase detector). I can't see a benefit to a dead zone in frequency synthesis PLLs but say for a motor servo PLL the motor would be off in the dead zone which could help reduce hunting and thus power consumption.

Ray

 

[chuckey]

If the output from a phase lock loop is zero, then it can't be controlling anything. It could be 0V, midway between a + and a - voltage but this represent that it's at midway not it's zero.
Frank

 

[biff44]

In the dead zone, nothing comes out of the charge pump. So also there are also no clock spurs imparted onto the oscillator. I suppose if one had a very stable oscillator (like a vcxo) and you wanted the absolute minimum of spurious output and did not mind a little bit of random walk in phase, you could design a bigger dead zone deliberately and have the PLL work there.

But if you had that stable of a VCO...you could just use a 10 Hz loop bandwidth, and achieve the same thing thru the control loop's lowpass response. You could have 100+ dB of active and passive filtering of clock spurs, for instance. The disadvantage is a long lock tme.

So I guess if you need no spurs, and a fast lock time....maybe.i

 

[chuckey]

If there are "clock spurs" imparted to the oscillator it would have disastrous clock frequency side bands. Proper PLLs have a fast frequency locking loop and a slower phase locking loop, so one gets a better compromise between lock-up speed and phase noise.
Frank

 

[biff44]

EVERY PLL in the world has clock spurs on either side of the carrier output. It is just a matter of how far down they are. With a deadzone, for some short period of time (maybe a few tens of mS with a high Q VCXO), there would be no clock spurs.