Aimerbhat
Newbie level 5
hello every1
I made a design which has 5 divided(internal) clks(clkby2,clkby4 etc) derived from main clk by a counter.
i am synthesizing it via DC specified the divided clocks by create generate clk and main clock by create clk commands and there respective constraints wrt to main clk & divided clocks like edge etc
Now after synthesis when i do check_timing it gives a warning that ' derived clocks
(clkby2,clkby4 etc) are not linked with master clock "TIM-204
and most of the paths are also unconstrained
I am not able to figure out is this problem.
How can i link master clock with other clocks and make paths constrained
please reply
thanks in advance
I made a design which has 5 divided(internal) clks(clkby2,clkby4 etc) derived from main clk by a counter.
i am synthesizing it via DC specified the divided clocks by create generate clk and main clock by create clk commands and there respective constraints wrt to main clk & divided clocks like edge etc
Now after synthesis when i do check_timing it gives a warning that ' derived clocks
(clkby2,clkby4 etc) are not linked with master clock "TIM-204
and most of the paths are also unconstrained
I am not able to figure out is this problem.
How can i link master clock with other clocks and make paths constrained
please reply
thanks in advance