rmmy
Newbie level 3
Is it possible in Verilog/System Verilog to inetrconnect with a single net different signals of (different vector widths) of different instantiations?
when I tried this code in ModelSim I dont get any compilation error. But with VCS I am getting compilations error. I want to know if it is allowed?
the error with VCS simulator I get is:
7/Error-[IMCPC] Illegal multiconcat port connect
7/ multi-concat cannot be used on the high-conn
7/ of a inout or out port
7/ {4 {clk}}
7/Error-[IMCPC] Illegal multiconcat port connect
7/ multi-concat cannot be used on the high-conn
7/ of a inout or out port
7/ {4 {clk}}
Sample Code is as follows:
module top (
input/output declarations
);
wire clk;
cksysinthspinetbr icksysinthspinebrp (
.ckuclksysintgdtbl ({4{clk}}),//"ckuclksysintgdtbl" is 4-bit signal
.ckuclksysintgdtbr ({90{clk}}),//"ckuclksysintgdtbr" is 90-bit signal
.hopin (pguclks15b[20:11] ),
.pguclks16tbr(pguclks16tbr),
.pguclks17mtbr(pguclks17mtbr)
);
//------------------------
cksysinthspinetbr icksysinthspinetrp (
.ckuclksysintgdtbl ({4{clk}}),// "ckuclksysintgdtbl" is 4-bit signal
.ckuclksysintgdtbr ({90{clk}}),// "ckuclksysintgdtbr" is 90-bit signal
.hopin (pguclks15t[20:11] ),
.pguclks16tbr(pguclks16tbl),
.pguclks17mtbr(pguclks17mtbl)
);
endmodule
when I tried this code in ModelSim I dont get any compilation error. But with VCS I am getting compilations error. I want to know if it is allowed?
the error with VCS simulator I get is:
7/Error-[IMCPC] Illegal multiconcat port connect
7/ multi-concat cannot be used on the high-conn
7/ of a inout or out port
7/ {4 {clk}}
7/Error-[IMCPC] Illegal multiconcat port connect
7/ multi-concat cannot be used on the high-conn
7/ of a inout or out port
7/ {4 {clk}}
Sample Code is as follows:
module top (
input/output declarations
);
wire clk;
cksysinthspinetbr icksysinthspinebrp (
.ckuclksysintgdtbl ({4{clk}}),//"ckuclksysintgdtbl" is 4-bit signal
.ckuclksysintgdtbr ({90{clk}}),//"ckuclksysintgdtbr" is 90-bit signal
.hopin (pguclks15b[20:11] ),
.pguclks16tbr(pguclks16tbr),
.pguclks17mtbr(pguclks17mtbr)
);
//------------------------
cksysinthspinetbr icksysinthspinetrp (
.ckuclksysintgdtbl ({4{clk}}),// "ckuclksysintgdtbl" is 4-bit signal
.ckuclksysintgdtbr ({90{clk}}),// "ckuclksysintgdtbr" is 90-bit signal
.hopin (pguclks15t[20:11] ),
.pguclks16tbr(pguclks16tbl),
.pguclks17mtbr(pguclks17mtbl)
);
endmodule