blowfish
Member level 4
I have a digitally controlled delay circuit but i dont know how to implement it using the Verilog HDL tool , as it has added capacitor in the bottom. Anyone please send me the procedure or codes to implement it.I am attaching the paper in which it is shown the circuit ...
(Clock Deskew Buffer Using a SAR Controlled Delay Locked loop)
(Clock Deskew Buffer Using a SAR Controlled Delay Locked loop)