How to implement derivative, and create a delay of dozens of clock cycles?

[sarit8]

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I have uart entity which have the following signals (I write only the relevant - for tx)

-- The output data: 8 bit - this is the UART receiver
-- Data is only valid during the time the STB is high
-- Acknowledge the data with a pulse on ACK, which is confirmed by
-- revoking STB.
-- When the following start bit is received the data becomes
-- invalid and the STB is revoked. So take care about fetching the
-- data early enough, or install your own FIFO buffer
DATA_STREAM_OUT     : out std_logic_vector(7 downto 0);
DATA_STREAM_OUT_STB : out std_logic;
DATA_STREAM_OUT_ACK : in  std_logic;
TX                  : out std_logic;

I have another block which its enable input should changed to high for only one clock when there is a change of the DATA_STREAM_OUT_ACK (high to low) plus delay of 50 clk cycles.

I guess I should derive DATA_STREAM_OUT_ACK, but I'm not sure hot to implement this, and also the delay (may be with counter).

 

[barry]

I would probably use a state machine. Basically: The falling edge of DATA_STREAM_OUT_ACK would force a transition out of the idle state and enable a counter. When the counter timed out the FSM would generate a single cycle pulse and return to idle.