u24c02
Advanced Member level 1
Hi i have some questuon about i2c clock domain switching to system clock
Currentlly, i use AHB lite system and i'm trying to add i2c slave in AHB Lite system.
Here is question.
How can i handle i2c scl clock between AHBsystem's clock domain ?
especially, i willing to move date from i2c to ahb lite system data bus
So, how can i get safefully data from i2c to system ahb lite system without cdc problems?
Especially, what is espectate in verilog rtl design?
Currentlly, i use AHB lite system and i'm trying to add i2c slave in AHB Lite system.
Here is question.
How can i handle i2c scl clock between AHBsystem's clock domain ?
especially, i willing to move date from i2c to ahb lite system data bus
So, how can i get safefully data from i2c to system ahb lite system without cdc problems?
Especially, what is espectate in verilog rtl design?