How to give input in Xilinx ISE software

[moonnightingale]

I have written this code in xilinx

module mux(mux_out,data_1,data_2,select);
parameter word_size=32;
output [word_size-1:0] mux_out;
input [word_size-1:0] data_1,data_2;
input select;
assign mux_out=select?data_1:data_2;
endmodule

I am able to synthesize and view RTL Schematic but i will be highly grateful if some body tells me the method that how can i feed input to it and see the actual result and waveform. Kindly explain in detail

 

[permute]

write a testbench. look online for examples. from there you can use a simulator. isim is included with ISE Webpack.

 

[moonnightingale]

I have no idea what is test bench
Can u do explain all these to me with this simple example

module bitcompar(A_lt_B,A_gt_B,A_eq_B,A0,A1,B0,B1);
input A0,A1,B0,B1;
output A_lt_B,A_gt_B,A_eq_B;
assign A_lt_B=({A1,A0}<{B1,B0});
assign A_gt_B=({A1,A0}>{B1,B0});
assign A_eq_B=({A1,A0}=={B1,B0});
endmodule

how can i check it

 

[Jack// ani]

This should you to get it right: Art of Writing TestBenches Part - I