how to get the max freqency ?

[sevid]

hi,everyone

my Q is how to get the max freqency of ur design from the synthesis results of DC ?

from the "data arrival time" ?
but i find that there are different "data arrival time"s when different clock cycles are set in ur tcl scripts, and all of these different clock cycles may meet the timing constaints from the timing report of DC.
but they have different "data arrival time"s, and i dont know which one to be selected as my max frequency. The one that equals to the "data required time" ?

what can i do then ?

plz

thanks

sevid

 

[dcreddy1980]

The worst timing path from reg - reg path will give you an idea about your max frequency. if you have used flip flops with proper naming i.e all of them ending with "_reg" extension, You can use the following also to get the worst path :

report_timing -from *_reg/* -to *_reg/*

If you know u r clock pin and data pin name, replace them in the above command

Regards,
dcreddy

 

[iwpia50s]

Also from your STA slack report. If you have negative slack then you have exceeded the max freq. If you have positive slack then you can decrease you clock period. The data arrival time is the time it takes for the data to propagate to the input of a clocked element.

 

[ljxpjpjljx]

you should make sure your hold time and setup time both meet your condition!