how to get gate-leve netlist when synthesis with DC

[feel_on_on]

how to get gate-leve netlist when synthesis with Design Compiler?
I need to make a post-simulation

 

[jeffleeh]

use DC command:
write -h -format verilog -output xxx.v

 

[rameshsuthapalli]

Hi all,

You can write out the netlist following way
set design $TOP #$TOP is toplevel design.
write -h -f verilog -o ${TOP}.v

you can't use it for the post-simulationstiming but you can use it for the post-simulations functional.
since it don't have the clock and reset tree's.the delay and load on these net's will be more.

regards,
ramesh.s

 

[feel_on_on]

thanks,but how to get post-simulation gate-level netlist ? after P&R,then...save this gate-level netlist ?

 

[rameshsuthapalli]

Hi,

yes, you need to get the P&R netlist for the post-simulation for timing along with the SDF in required formate.

regards,
ramesh.s

 

[rsrinivas]

hi feel_on_on
wat i think is u r accustomed to the fpga flow(if i am right xilinx ise) and u r trying to link it with asic flow.
in asic a single tool cannot perform everything as in an fpga flow.
check out the dc reference guide which gives u a good insight into the flow.
good luck
regards
srinivas