zhangljz
Member level 5
Hi,
I have a problem with modelsim and RTL compiler that not all the possible warning is generated. For example when I simulate and synthesize this code:
module a_test (
input [5:0] in_a,
input [3:0] in_b,
output c
);
assign c = ( in_a==in_b)? 1 : 0;
endmodule
Then the tools will treat it as (in_a == {2'b0, in_b}) ? 1 : 0
But, what I want is to generate warning for all the mismatching connection or comparison etc, so we know where there are this kind of mismatching and we can decide which are acceptable and which are bugs.
Anybody knows?
Thanks.
I have a problem with modelsim and RTL compiler that not all the possible warning is generated. For example when I simulate and synthesize this code:
module a_test (
input [5:0] in_a,
input [3:0] in_b,
output c
);
assign c = ( in_a==in_b)? 1 : 0;
endmodule
Then the tools will treat it as (in_a == {2'b0, in_b}) ? 1 : 0
But, what I want is to generate warning for all the mismatching connection or comparison etc, so we know where there are this kind of mismatching and we can decide which are acceptable and which are bugs.
Anybody knows?
Thanks.