How to generate a short pulse from a longer pulse

[henry kissinger]

I have a pulse of 10 nesc wide. (low 0V, high 1V)
How do I build a circuit that take this 10 nsec pulse and output a pulse much smaller (<1 nsec)?
The rise point of the 10 nsec pulse and the <1 nsec pulse should be almost the same (<1 nsec difference)
any ideas?

 

[KlausST]

Hi,

generally a monoflop. Maybe a non retriggerable monoflop.

For these short pulses i'd try to feed the signal in two paths to an AND gate:
* one path directly to the AND gate
* the other path via an inverter to the AND gate.

The delay time of the inverter path determines the pulse width.
If the pulse now is too narrow, then add an RC in front of the inverter to delay the signal even more.

Klaus

 

[danadakk]

Differentiator :

RC-positive edge detector

I want to build a simple edge detector that triggers an interrupt once the power adapter is hot-plugged. Therefor IN will be around 18V and on the output I need 1V8 logic. The generated pulse does...

electronics.stackexchange.com

https://www.edaboard.com/threads/i-need-to-detect-rising-edge-of-pulse.270878/

How to generate edge-triggered pulse

First, a bit of background: I am just a hobbyist with electronics and have very little formal education in the area. I understand most terminology, but generally require a schematic for me to be ab...

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The above are general ideas, but applying at 1 nS challenging. How repeatable do
you need this over T and V, eg. accuracy ?

Tunnel diode for sure can do this. ECL logic.....

Some seriously fast logic - https://www.analog.com/en/parametricsearch/10749#/


Regards, Dana.

--- Updated Oct 20, 2022 ---

Note, the designs that show a large C attached to the input of a CMOS gate
should add a series R between the gate input and C to prevent potential
logic gate damage on p ower loss.

Regards, Dana.

 

[FvM]

The rise point of the 10 nsec pulse and the <1 nsec pulse should be almost the same (<1 nsec difference)

Not possible without replicating the 10 ns pulse and using the replicated instead of the original pulse, at least with regular logic gates.

 

[danadakk]

Time delay (read gate delay) could solve that. Not exactly a precision approach.

That of course cause latency.....and T and V error sensitivity.


Regards, Dana.

 

[volker@muehlhaus]

The rise point of the 10 nsec pulse and the <1 nsec pulse should be almost the same (<1 nsec difference)

You can use a shorted delay line (reflection factor = -1) to cancel the signal, leaving only a narrow pulse. Pulse width is defined by round trip delay. The downside of this simple solution is that you get not only the first (desired) reflection but additional multi-path reflections with lower amplitude.