How to generate a pi/4 phase delay?

[hbsustc]

phase delay clock

Hello, everyone. I have an old Atera FPGA, there isn't any PLL on it. Now I have a reference clock about 10MHz, the problem is how to generate another reference clock whose phase leads the former by 45 degrees, or lags the former by 45 degrees? It seems I have to use code to realize it. Thank you in advance!

 

[FvM]

I see two options, assuming you have no additional clocks.
1. Generate an about 12.5 ns delay by a logic-cell delay line.
2. Design a ring oscillator clocking a digital delay circuit.

In both cases, synthesis attributes are required to prevent the HDL tool from removing delaying logic cells. The respective tool manuals tell, how to.

 

[hbsustc]

Thank you for your suggestions, FvM, I'm afraid its performance will be deteriorated by the following points:
1. For the Logic-cell delay line, its delay is not accurate, it will be influenced by power-supply and temperature.
2. The 3-stages ring oscillator realized in FPGA seems not feasible, it's a little unstable for a long term utilization.

This afternoon, I tried to use the following way to realize pi/4 lead or lag phase delay:

1. Use a 10MHz*8=80MHz clock to trigger one Gray Code counter (I tried to use Binary counter firstly, but the glitch sucks)
2. The output of Gray Code counter will be 1, 3, 2, 6, 7, 5, 4, 0 periodically, so write something to make the module generate a pulse when the output=1 or output=7. (Generates other 2 pulses when the output=3 or 5 and output=2 or 4)
3. Use the pulses to trigger a frequency devider.

So it generates three clock signals whose phase are pi/4 lead, 0, pi/4 lag.

 

[FvM]

Yes, an additional clock would allow a more precise solution. But it has a delay variation/uncertainty of one period of the high frequency clock, if both clocks are unrelated. It would need a much higher frequency multiply to reduce the uncertainty to an acceptable amount. A delay line may achieve a higher phase accuray than an unrelated auxilary clock, which less effort.

 

[hbsustc]

Yes, you are right. Real time delay of LE buffers can't be got from timing simulation, normally it is smaller than the simulated value. So I need to program the chip and measure it. Thank you!