Chan-Hsiang Weng
Newbie level 2
when I simulate the circuit, and plot the gm/Id vs. Id/W, th Vds should be fixed.
but how to fix it?? my simulation conditions is tsmc18rf and use a single nmos.
Vdd=1.8V, Ib=2mA, RL=159, C=10pF, just the same condition with Boris handout
but different process, how should I do to fix vds ?? just plus a ideal vds between
drain and source ?? I feel this is unreasonable. could someone can answer me the
question? thanks
but how to fix it?? my simulation conditions is tsmc18rf and use a single nmos.
Vdd=1.8V, Ib=2mA, RL=159, C=10pF, just the same condition with Boris handout
but different process, how should I do to fix vds ?? just plus a ideal vds between
drain and source ?? I feel this is unreasonable. could someone can answer me the
question? thanks