how to fix hold and setup at gated andnon gated clock

[bhaskarg]

dear all,

if i have 2 flip-flops ,
ff1 clock pin is connected to clk
ff2 clock pin is connected to gated clock.....

my doubt...
if i found either hold r setup violation on this path with repsect to +ve edge.. then how i can fix the violation

can any one guide me


thanks in advance
bhaskarg

 

[HTA]

A circuit an timing diagram would be needed to understand your problem. If setup and hold time violation can not be avoided(asychronous incoming signals) a synchronization with two flipflops in series could be used. The second flipflop uses a delayed clock, so that metastable states of the first flipflop a over.

Enjoy your design work!

 

[bhaskarg]

thanks HTA....


one more doubt

what is the use of amobea view in the ENCOUNTER cadence

thanks in advance