asic_architect
Newbie level 6
I am getting following errors in check_timing_intent. Is there a way to fix them in Genus? Or I have to change the RTL?
Lint summary
Unconnected/logic driven clocks 0
Sequential data pins driven by a clock signal 0
Sequential clock pins without clock waveform 10
Sequential clock pins with multiple clock waveforms 475
Generated clocks without clock waveform 0
Generated clocks with incompatible options 0
Generated clocks with multi-master clock 0
Paths constrained with different clocks 0
Loop-breaking cells for combinational feedback 0
Nets with multiple drivers 0
Timing exceptions with no effect 0
Suspicious multi_cycle exceptions 0
Pins/ports with conflicting case constants 0
Inputs without clocked external delays 22
Outputs without clocked external delays 95
Inputs without external driver/transition 22
Outputs without external load 95
Exceptions with invalid timing start-/endpoints 0
Total: 719
Lint summary
Unconnected/logic driven clocks 0
Sequential data pins driven by a clock signal 0
Sequential clock pins without clock waveform 10
Sequential clock pins with multiple clock waveforms 475
Generated clocks without clock waveform 0
Generated clocks with incompatible options 0
Generated clocks with multi-master clock 0
Paths constrained with different clocks 0
Loop-breaking cells for combinational feedback 0
Nets with multiple drivers 0
Timing exceptions with no effect 0
Suspicious multi_cycle exceptions 0
Pins/ports with conflicting case constants 0
Inputs without clocked external delays 22
Outputs without clocked external delays 95
Inputs without external driver/transition 22
Outputs without external load 95
Exceptions with invalid timing start-/endpoints 0
Total: 719