How to extract RLC circuit from s-parameter touchstone file in ADS?

[wan1235/*-1-]

Everyone, I would like to ask, there is currently a known S-parameter for a 2-port network, and a model file close to the S-parameter has been generated through the wideband SPICE model of ADS. （.sp2,.sp3,.hsp,.hsp）
But how do you use these files to convert them into corresponding RLC circuits or more complex component circuits? Here are the documents obtained.

.SP2：
* Momentum eesofbbs_64 2022.00 (*) built: Jul 2 2021
**************************************************

* RLC admittance subckt

.SUBCKT bbs_RL_main 1 2 3

X1 1 3 bbs_RL_id_1_1
X2 2 3 bbs_RL_id_2_2
X3 2 1 bbs_RL_id_2_1

.ENDS bbs_RL_main
**************************************************


.SUBCKT bbs_RL_id_1_1 1 2

Rgs 1 2 5.00000000000000e+01

Rre1 1 10001 1.04846705084131e-01
Lre1 10001 2 4.53866569122965e-09

Rco2 1 12 -1.22951940170065e+02
Lco2 12 22 8.56793345142387e-09
Cco2 22 2 6.38685779263559e-14
RGco2 22 2 1.07754867125530e+03

Rre3 1 10003 -2.72922003692118e+20
Lre3 10003 2 -1.18537624402029e+13

Rco4 1 14 7.51523839890950e+23
Lco4 14 24 5.53833940683497e+12
Cco4 24 2 9.03847957116950e-36
RGco4 24 2 -8.17225035349824e+23

.ENDS bbs_RL_id_1_1
**************************************************


.SUBCKT bbs_RL_id_2_2 1 2

Rgs 1 2 5.00000000000000e+01

Rre3 1 10003 1.03666977501187e-01
Lre3 10003 2 4.50254544363957e-09

Rco4 1 14 -1.78464545052696e+02
Lco4 14 24 9.11849751545625e-09
Cco4 24 2 5.49654477833988e-14
RGco4 24 2 9.14975239401263e+02

.ENDS bbs_RL_id_2_2
**************************************************


.SUBCKT bbs_RL_id_2_1 1 2

Rre3 1 10003 2.72922003692118e+20
Lre3 10003 2 1.18537624402029e+13

Rco4 1 14 -7.51523839890950e+23
Lco4 14 24 -5.53833940683497e+12
Cco4 24 2 -9.03847957116950e-36
RGco4 24 2 8.17225035349824e+23

.ENDS bbs_RL_id_2_1
**************************************************




.SP3：
* Momentum eesofbbs_64 2022.00 (*) built: Jul 2 2021
**************************************************

***************************************

*bbspice subcircuit with consecutive port numbers.
.SUBCKT bbspice_RL_subckt port_1 port_2 gnd_0

* PORT_1
vi_1 port_1 _net_1 0.00000000000000e+00
vb_1 _net_4 _net_5 0.00000000000000e+00
R_Z0_1 _net_1 _net_2 5.00000000000000e+01 NOISE=0
H_b_1 _net_2 gnd_0 vb_1 1.41421356237310e+01
E_v_1 _net_3 gnd_0 port_1 gnd_0 7.07106781186548e-02
H_i_1 _net_4 _net_3 vi_1 3.53553390593274e+00


G_C_1_1 _net_5 gnd_0 _net_11 gnd_0 -5.38906622390914e+09
G_C_1_2 _net_5 gnd_0 _net_12 gnd_0 -1.51850852015771e+09
G_C_1_3 _net_5 gnd_0 _net_13 gnd_0 6.07135769798283e+07

* PORT_2
vi_2 port_2 _net_6 0.00000000000000e+00
vb_2 _net_9 _net_10 0.00000000000000e+00
R_Z0_2 _net_6 _net_7 5.00000000000000e+01 NOISE=0
H_b_2 _net_7 gnd_0 vb_2 1.41421356237310e+01
E_v_2 _net_8 gnd_0 port_2 gnd_0 7.07106781186548e-02
H_i_2 _net_9 _net_8 vi_2 3.53553390593274e+00


G_C_2_4 _net_10 gnd_0 _net_14 gnd_0 -5.34473317473444e+09
G_C_2_5 _net_10 gnd_0 _net_15 gnd_0 -1.47468069282052e+09
G_C_2_6 _net_10 gnd_0 _net_16 gnd_0 2.28657572493179e+08

* STATE_1
C_1 _net_11 gnd_0 1.00000000000000e-11
G_A_1_1 _net_11 gnd_0 _net_11 gnd_0 5.44409332213270e-02
G_B_1_1 _net_11 gnd_0 _net_4 gnd_0 -1.00000000000000e-11

* STATE_2
C_2 _net_12 gnd_0 1.00000000000000e-11
G_A_2_2 _net_12 gnd_0 _net_12 gnd_0 1.59259445248501e-02
G_A_2_3 _net_12 gnd_0 _net_13 gnd_0 -4.05275594411085e-01
G_B_2_1 _net_12 gnd_0 _net_4 gnd_0 -2.00000000000000e-11

* STATE_3
C_3 _net_13 gnd_0 1.00000000000000e-11
G_A_3_3 _net_13 gnd_0 _net_13 gnd_0 1.59259445248501e-02
G_A_3_2 _net_13 gnd_0 _net_12 gnd_0 4.05275594411085e-01

* STATE_4
C_4 _net_14 gnd_0 1.00000000000000e-11
G_A_4_4 _net_14 gnd_0 _net_14 gnd_0 5.44409332213270e-02
G_B_4_2 _net_14 gnd_0 _net_9 gnd_0 -1.00000000000000e-11

* STATE_5
C_5 _net_15 gnd_0 1.00000000000000e-11
G_A_5_5 _net_15 gnd_0 _net_15 gnd_0 1.59259445248501e-02
G_A_5_6 _net_15 gnd_0 _net_16 gnd_0 -4.05275594411085e-01
G_B_5_2 _net_15 gnd_0 _net_9 gnd_0 -2.00000000000000e-11

* STATE_6
C_6 _net_16 gnd_0 1.00000000000000e-11
G_A_6_6 _net_16 gnd_0 _net_16 gnd_0 1.59259445248501e-02
G_A_6_5 _net_16 gnd_0 _net_15 gnd_0 4.05275594411085e-01


.ENDS bbspice_RL_subckt
***************************************


***************************************
* S-based subckt


*bbspice subcircuit with external port numbers.

.SUBCKT bbspice_RL 1 2 0

x_ 1 2 0 bbspice_RL_subckt

.ENDS bbspice_RL
***************************************

 

[BigBoss]

This file can be imported into ADS schematic.

 

[wan1235/*-1-]

This file can be imported into ADS schematic.

I tried importing this file into schematic, but it turned out to be like a use of symbol, no concrete RLC circuitry.

 

[volker@muehlhaus]

no concrete RLC circuitry

These broadband SPICE extractions do not provide nice human-readable RLC circuits. The nice RLC equivalent circuits that we sometime see are really hand-made.

For transmission line models, we know that cascaded RLGC segments are suitable, and you can export the corresponding values for one frequency.

 

[wan1235/*-1-]

These broadband SPICE extractions do not provide nice human-readable RLC circuits. The nice RLCG equivalent circuits that we sometime see are really hand-made.

For transmission line models, we know that cascaded RLGC segments are suitable, and you can export the corresponding values for one frequency

Yes, I have exported a concrete S-parameter curve for the simulation, the red is the ideal model, and the blue is the ADS simulation results.
So if I want to get the actual circuit model, do I have to read the SPICE model material and design it myself based on these files?

 

[volker@muehlhaus]

So if I want to get the actual circuit model, do I have to read the SPICE model material and design it myself based on these files?

Yes, if there is anything readable in the SPICE file, and not just controlled sources. Or even better: create it based on your understanding of the physical structure.

Simpe example: the model of a printed inductor would have series L and series C, some shunt capacitance and some capacitance between the turns. That is for an "electrically small" model, models that are physically large (in terms of conductor length vs. wavelength) might require some cascaded segments which makes the overall model more complex.

 

[wan1235/*-1-]

Yes, if there is anything readable in the SPICE file, and not just controlled sources. Or even better: create it based on your understanding of the physical structure.

Simpe example: the model of a printed inductor would have series L and series C, some shunt capacitance and some capacitance between the turns. That is for an "electrically small" model, models that are physically large (in terms of conductor length vs. wavelength) might require some cascaded segments which makes the overall model more complex.

Okay, thank you, I'll start trying to read the logic of the SPICE model and design the circuit myself