skyworld_cy
Junior Member level 3
Hi,
I have a design with Verilog, simulated with irun. Is there a way to extract the hierarchy of the design? I would like to extract all ports of each level and probe them. thanks.
regards
skyworld
I have a design with Verilog, simulated with irun. Is there a way to extract the hierarchy of the design? I would like to extract all ports of each level and probe them. thanks.
regards
skyworld