how to estamate pad capacitance and pcb routing capacitance

[lhlbluesky]

how to estimate pad capacitance and pcb routing capacitance

for 0.18 um technology (tower), in general, what is the capacitance of an analog pad? can it be in the order of pF? 1pF, 2pF, 3pF, or any other value?

besides, for a 20mm-long wire in pcb board, in general, what is its equivalent resistance and capacitance? can it be 50 ohm and 1pF? or any other value?

please help me, and explain to me more about this, i really need your help, thanks all, thanks.

 

[dick_freebird]

Lot of variables in pad construction. Some flows use a stack
of every metal layer with interlevel contacts, for wirebond.
But bump bond pads may be only the uppermost layer. Those
details make a big difference in "t" for the plate capacitance.

Then there is the question of raw size - I see everything from
250 um (using heavy wire for power apps) to <25um (area array
imager readout ICs, direct bump bond). That's your "A".

Your pad may sit over substrate or a well region, which will
determine -to what- the capacitance returns stray signal.

If Tower/Jazz has provided you the PDK there should at
least be standard pad info, although they are less willing to
share vertical construction details you could probably figure
out the bottom-most layer used in your pad of interest
and get areal capacitance (and fringe?) from the PDK for
that layer.

PCB traces can be designed for 50-ohm -impedance- but
resistance will be way less. Trace thickness you get to
specify when you order, length & width you draw, PCB
vendor may tell you resistivity (if not, Wiki will give you
a raw value I'm sure). Similarly you can get the PCB inter-
layer dimension and dielectric constant from your vendor
(or prospective vendors). There are a lot of options that
are degrees-of-freedom in the capacitance result.

 

[lhlbluesky]

thanks very much.