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Assuming that you mean the AC waveform output, the standard way to do this is to have the basic VCO at twice the desired frequency and use a divide by two logic circuit. One example is a D flip flop with the Qnot output connected to the D input. Then clock it with your 2x frequency VCO.
Include into your design :2 (division by 2) circuit and this will ensure that output wave has exactly 50% duty cycle.
Division by 2 circuit can be simple D-FlipFlop where you connect negative output to D-input or JK-FlipFlop with bothe J and K inputs connected to Ligic H.
you may need a D-flip flop, however, you should pay more attention to the structure, since it works at high speed, so you may need a other structure to implement such a frequency device.
One of the best thing I found for PLL was spectreVerilog simulator included in cadence IC environment. But this is true only if you have complex PLL with large digital core. In such case you can replace analog components (VCO, PFD, Charge pump ....) with veriloga model, and use verilog model for digital cell. This will allow you to evaluate structure in minutes instead of days.
Generaly behavioural modeling of the components that are not under test will cut down significantly your simulation time.
For the full transistor level simulation you can use hsim, it has decent accuracy but is VERY fast (about 4-5 times faster then spectre simulator for PLL case, they claim it is 40 X faster in digital circuit simulations). There is also ultasim and some simulator from synopsis, but I never used either of those.
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