jamesyang1209
Full Member level 1
modelsim fsdb
Dear Group,
I am using modelsim for simulation. I can dump fsdb file (for debussy) by writing some statement in verilog code. But I don't know how to write a stement to do that in VHDL code. Please tell me.
Thanks in advance.
Dear Group,
I am using modelsim for simulation. I can dump fsdb file (for debussy) by writing some statement in verilog code. But I don't know how to write a stement to do that in VHDL code. Please tell me.
Thanks in advance.