How to do ROM synthesis model

[mitchell]

Dear All :
Does anyone know how to do the synthesis model of ROM , We use the
ROM-Compiler to generate the GDS ,CDL ,.lib files , But we export it from
0.15um to 0.18um . So that we don't have the lib files for synthesis ,
Does any one know how to do the synthesis model ( .lib ) or Analog
Circuit's look-up table . Thanks

 

[CatKing]

re-simulate the cdl with new spice model, get the timing and fill in to the old .lib