How to do LVS for a digital design

[Greatrebel]

Hi All,

I am designing PnR for a digital chip using Encounter. Currently we do not have GDS files but LEF files for std cells from vendor. I am wondering how I can do LVS check in Encounter. Or do I need to use other tools like Assura to do LVS? Since I do not have schematic, whehter I need to convert the netlist into schematic, and which netlist I should use for the convertion, the one I used as design import for PnR or the one generated by Encounter after routing?

Thanks in advanced

 

[amanyuny]

First of all, you should get two files of std cells from your vendor : First, gds file to streamIn to your layout view(Laker) as a refenence library. Second, spice file to included in when doing LVS(calibre).

Using your P&R datebase to get final gds and streamIn to layout view with reference library of std cell.
Using your P&R database to get final physical netlist and "v2lvs" command (calibre) to conver netlist to schematic.
Then you can do LVS by using above gds and schematic.

 

[Greatrebel]

hi amanyuny，

Thank you very much for your reply. I have already gotten the gdf streamed into Virtuso and netlist converted into DFII. But when I run LVS by Assura, it failed, becuase Errors exist in the rules file './extract.rul'. There is an unbound value called SCraw. It is the first time I use Assura LVS. Could you please give me any help on this.

Thanks again