irun2
Member level 2
Hi all,
It's a simple 16x16 multiplier and it's used for test only. After first compile I used the command pipeline_design to retime that mul.
And a default.svf was created. In formality environment, I imported the svf file and rtl, db library, and gate netlist, and set top module respectively.
There're points mismatched as the clock port is added, so and I ignored them and went ahead to do verify.
The verification was failed too. After analyzed the points, formality gave the following recommandation:
Description - Rejected Guidance Command:
The rejection of some SVF guidance commands will almost invariably
cause verification failures. For more information use:
'report_svf_operation -status rejected -command command_name
Recommendations:
retiming_finished
What should I do next? Had I missed some steps in the setup pane?? Somewhat I think it's related to the dware resource being used during compilation... but I don't know what information formality needs...
---------- Post added at 03:17 ---------- Previous post was at 03:15 ----------
I've read the thread https://www.edaboard.com/threads/79278/, but we used different tools
It's a simple 16x16 multiplier and it's used for test only. After first compile I used the command pipeline_design to retime that mul.
And a default.svf was created. In formality environment, I imported the svf file and rtl, db library, and gate netlist, and set top module respectively.
There're points mismatched as the clock port is added, so and I ignored them and went ahead to do verify.
The verification was failed too. After analyzed the points, formality gave the following recommandation:
Description - Rejected Guidance Command:
The rejection of some SVF guidance commands will almost invariably
cause verification failures. For more information use:
'report_svf_operation -status rejected -command command_name
Recommendations:
retiming_finished
What should I do next? Had I missed some steps in the setup pane?? Somewhat I think it's related to the dware resource being used during compilation... but I don't know what information formality needs...
---------- Post added at 03:17 ---------- Previous post was at 03:15 ----------
I've read the thread https://www.edaboard.com/threads/79278/, but we used different tools