how to do ECO for a design?

[feel_on_on]

how to do ECO for a design? what eda tools ?

Thanks

 

[linuxluo]

hi,
the best way is to do it manually.
yes, in current eda tools there exist eco place/ eco route.
but most of important is how do you keep your netlist almost the same after eco. so synthesis is not prefered .

 

[odeafeiner]

If you want to get some idea, you can try to use altera Quartus tools to see
some ECO experience.

 

[straw]

there are many method,in general,every vendor has their own tools, but you can write the eco script

 

[srkumar81]

There are several stages for ECO. First if in ur design only there is eco routing. This is metal eco. All P&R tools support this. u can do this by using manual routing. The next one in ur netlist only few combo changes. There u have to do eco placement followed by routing. If there is change in sequential elements then ur eco is going to be very difficult as you will face very hard to fix setup and hold in ur design. If more cells changes the it is not eco. u have to do ur entire design again.

 

[skymusic]

After synthesize, you can eco to modified the netlist. But you had better to modify RTL not modify netlist directly.
After place, to fix timing violation(setup), you can eco(insert buffer, resize cell, etc.), Now, any P&R tools can do it.
After route, you can eco(modify route, and insert buffer, resize cell, etc.), too.

 

[zhangpengyu]

find the bug, change RTL, and simulation.
change the netlist.
do formal verification between netlist and RTL.
Then backend will do .......