How to DFT for design with scan_mode is not a primary input

[wkong_zhu]

In my design, scan_mode(TEST_MODE) is a internal register output pin, I have no more pin dedicated for scan_mode function, because the chip is PAD limited. Some one can help me. How to write script in DC and Teramax.

 

[eda_wiz]

you can multiplex normal mode I/O data pins for Test ip/op etc.. but atleast one extra pin is reqd for enabling testmode.

 

[leeenghan]

Re: How to DFT for design with scan_mode is not a primary in

Hi,

I think to DC there is no different if SCAN-ENABLE or TEST-MODE are dirven inside the chip or from the pad.

Regards,
Eng Han

 

[zhustudio]

HI wkong_zhu
I am not sure about your concern. But I will give my understanding of your question. There is two ways.

1. Seperate your DFT module from your scan_mode generation module. Sometime, your scanmod is generated from clock_gen or clock_mux or serial port. Commonly, this module is not on the scan chain. So for the scanned module. It must have a scanmode signals. Use set_test_hold to set this ports.
When you doing ATPG simulation, you can use a wrapper to instant your scanned module and scan mode signal generation module. It is top level scan simulation.

2. You can use set_case_analysis command to set scanmode to constant value in the internal pin. But it is not perferrable. So use method 1 is good one.

Good luck

 

[wkong_zhu]

Thank you, I have tried a method to add a pseudo test_mode pin in DC, then I modified synthesized netlist to remove the test_mode, and make internal test_mode net connect with that register output pin, then, I modify the SPF file, After that Teramax and generate pattern successfully, I use full scan method. It's so complicated! I have spent so much time doing that!