sajjad.hussain
Junior Member level 1
Dear All,
I have a design which uses a DCM to downscale my main clock to 5 more clocks. When I see the PAR timing report. It shows, different paths, how can I figure out that which path is actually is the critical path?
It also shows that:
Clock to Setup on destination clock clk_in
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_in | 25.219| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 3490153 paths, 0 nets, and 27939 connections
Design statistics:
Minimum period: 25.219ns{1} (Maximum frequency: 39.653MHz
That is critical path should be corresponding to 25.219ns path, but how to verify this from different paths shown in the timing report?
The timing report is attached herewith.
Regards
I have a design which uses a DCM to downscale my main clock to 5 more clocks. When I see the PAR timing report. It shows, different paths, how can I figure out that which path is actually is the critical path?
It also shows that:
Clock to Setup on destination clock clk_in
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_in | 25.219| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 3490153 paths, 0 nets, and 27939 connections
Design statistics:
Minimum period: 25.219ns{1} (Maximum frequency: 39.653MHz
That is critical path should be corresponding to 25.219ns path, but how to verify this from different paths shown in the timing report?
The timing report is attached herewith.
Regards