stoned
Member level 3
Hi all,
This osc feature is : output frequency is 1MHz~30MHz; and controlled by 5 bit , on the hand, has 32 steps between 1 and 30, for example 00000 correspond to 1M 11111 correspond to 30MHz.
first, i want to design this by VCO, and the control voltage of VCO is controlled by the 5 bits. But VCO output frequency's variation is too much for PVT.
when used PLL for output , variation is cancelled, but the cost is too much.
How to do this? can anyone give me some advice, thanks.
Stoned
This osc feature is : output frequency is 1MHz~30MHz; and controlled by 5 bit , on the hand, has 32 steps between 1 and 30, for example 00000 correspond to 1M 11111 correspond to 30MHz.
first, i want to design this by VCO, and the control voltage of VCO is controlled by the 5 bits. But VCO output frequency's variation is too much for PVT.
when used PLL for output , variation is cancelled, but the cost is too much.
How to do this? can anyone give me some advice, thanks.
Stoned