Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to design On-off keying using cascade configuration of MOS in ads software?

Status
Not open for further replies.

naqeeb93

Newbie level 4
Joined
Dec 16, 2022
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
107
I am using 50 MHz as a carrier signal and a pulse signal as the data signal. Unfortunately, I could not get my desired modulated ASK signal. I am using ADS software. Kindly guide me on how to do it. You can share related materials or papers. I have attached the modulated output with the pulse signal (5MHz) and carrier signal (100MHz). The output is very small. I do not know why?... as I was expected to get an output high when the data pulse signal is high and a low output when the data pulse signal is low. Kindly guide me on how can I improve my design?


enter image description here
1673255388817.png
1673255688973.png
 

You get out what you put in.

How did you arrive at component values? Output capacitor e.g. creates a highpass with 160 GHz cut-off frequency, also input capacitor and inductors are far-off from useful 50 MHz design.
 

thank you dear for your response. I got your point and changed the output RC value as per the requirement to pass the 50MHz modulated output. however still ac input signal has no impact on the output as I have changed the value of the AC input components also. could you guide what is wrong with the circuit?
1673271505825.png
1673271698451.png
 

Many changesd to the original circuit. I'll stop guessing at this point, the answer is at your finger tips. Check individual currents and voltages to see how far the signal propagates and where it's blocked in the circuit.
 

Because "Vhigh" voltage of the pulse generator is too low. If you increase it, the first MOS will be well biased.
You applied Vhigh=1V and consider Vgs voltage so that Vds voltage of the first MOS will be low to flow the current.
Delete caps and inductors first and observe the circuit as is.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top