how to design high frequency differential buffer?

[prcken]

i am doing a CML 2:1 divider with input clock frequency ranges from 2.3GHz to 3.6GHz (0.18um CMOS process), and CML latch has to be followed by an additional buffer to recover the logic level, however, by taking all loading capacitances into account, it's really hard to get some gain at higher frequency up to 1.8GHz. i need at least 2.5dB gain at high end frequencies.
any tricks to solve the problem? any experience and suggestions?
really appreciate.