How to design a frequency divide by 3 signal generator

[drewnity]

Hi!! I'm currently working on my project "FPGA based signal generator for digital communications". Not too sure how to get a frequency divided by 3 output. Is there any idea? I'm using block diagram to design my FPGA.

Any suggestions?

Thanks

 

[vhdl4u]

Basically you neead to generate a counter where it count 0, 1 and 2. So, your 2-bit counter output is /3. Now, pl. note that that output will not have 50% duty cycle. If you need 50% duty cycle then you need more circuit.

 

[user_asic]

Why not use the DCM?