how to design a clock multiplier in verilog

[ikru26]

verilog clock multiplier

can anyone give some details /outline of designing a clock multiplier in verilog.

 

[mkenobi]

clock multiplier verilog

vhdl code is available

http://www.eda.org/fmf/fmf_public_models/clock/cdc5801.vhd

 

[djalli]

clock multiplier in verilog

Homework?

 

[omid219]

vhdl clock multiplier

Do you have it's equivalent code in verilog?

 

[djalli]

clock multiplier vhdl

use a translator software

 

[eda_wiz]

vhdl code for clock multiplier

A synthesisable clock multiplier cant be implemented in verilog. well in actuall ckt you can use a 2 i/p xor gate with one input delayed by half (by adding delay buffers) for a x2 clock multiplier

I wonder whether you were thinking of clock dividers?????

 

[vipinlal]

here is a synthesisable frequency multiplier..
https://vhdlguru.blogspot.com/2010/04/combinatorial-frequency-multiplier.html

 

[voho]

you can use ip core in fpga look at DCM

 

[DaMoose]

if this is home work I cant answer it for you
if you are targeting an FPGA perhaps ..
there are DLL (Delay Lock Loop) modules that you can instantiate
giving 2x 4x etc ... clocks