tch77_pt75
Junior Member level 3
Hi Sinina, basically it is an experimentation whereby I am trying to drive this long wire of 3000um.
In my HPSICE simulation, I have tried to use a buffer( 2 inverters) with supply voltage of 1V to observe the impact of driving this long wire.
From the waveform, it is noted that it took 3ns for the signal to travel from one end of the wire to the other end when the logic changes from 0 to 1. As for 1 to 0, it takes about 500p-sec. The waveform looks just like the sawtooth waveform.
The size difference of the 1st(4.5um for PMOS) and 2nd inverter(9um for PMOS) is around 3x. The PMOS width ratio to NMOS width ratio is 2:1 and I have tried adjusting the ratio, up to 6:1, but it seems like it does not improved the response that much.
There is actually no device A and B at the moment as it is just my experimentation to observe and analyze this impact. I am also trying to figure out what is the best way to configure the buffer, ie. with 2 stage inverter or 4 stage inverter etc.
Any suggestion for the above?
In my HPSICE simulation, I have tried to use a buffer( 2 inverters) with supply voltage of 1V to observe the impact of driving this long wire.
From the waveform, it is noted that it took 3ns for the signal to travel from one end of the wire to the other end when the logic changes from 0 to 1. As for 1 to 0, it takes about 500p-sec. The waveform looks just like the sawtooth waveform.
The size difference of the 1st(4.5um for PMOS) and 2nd inverter(9um for PMOS) is around 3x. The PMOS width ratio to NMOS width ratio is 2:1 and I have tried adjusting the ratio, up to 6:1, but it seems like it does not improved the response that much.
There is actually no device A and B at the moment as it is just my experimentation to observe and analyze this impact. I am also trying to figure out what is the best way to configure the buffer, ie. with 2 stage inverter or 4 stage inverter etc.
Any suggestion for the above?
