How to design a Bandpass Filter using A FPGA?

[FreeSpirit]

its central frequecy is 4.2MHz Bandwidth 0.5MHz
stopband> 4.6MHz ;<3.8MHz
Passband ripple : 1dB
Minmum stopband attenuation:40dB

 

[eda4you]

its central frequecy is 4.2MHz Bandwidth 0.5MHz
stopband> 4.6MHz ;<3.8MHz
Passband ripple : 1dB
Minmum stopband attenuation:40dB

the easiest way is to use MatlabR14 hdl coder. It generates a code for instance for Xilinx FPGAs. What you need do include in your specs is the sampling frequency. Let's see, maybe I can send you the code!

 

[FreeSpirit]

My teacher haven`t told me the sampling frequency.
assuming it is 20MHz

can u send me the code??

thanks
my mail box is iamanewone@hotmail.com

 

[dewdrop]

You can also use the DSP Builder. It generates the code for instance to Altera FPGAs.

 

[mc_navman]

Um if someone sends u this code how will you learn. Do it yourself you may learn something.

 

[hoangthanhtung]

its central frequecy is 4.2MHz Bandwidth 0.5MHz
stopband> 4.6MHz ;<3.8MHz
Passband ripple : 1dB
Minmum stopband attenuation:40dB

You can find the code in the book "Digital signal process with FPGA" with Mayer.

 

[jay_ec_engg]

will u use xilinx or altera fpga ???
altera has good applicatin note with flex10k for filter designing....
i think for very first step, use matlab filter designtool. give ur spec. generate coefficient and quitze them......

fir codes are available easily( VHDL and Verilog) u can use VHDL Synthesis by K C CHang .. code is there... and fetch coefficient(quantized) from FPGA RAM. u will get filtered output.

in atlera site also fir code is there with scripting code also....

 

[eda4you]

My teacher haven`t told me the sampling frequency.
assuming it is 20MHz

can u send me the code??

thanks
my mail box is iamanewone@hotmail.com

 

[neocool]

You can also use the DSP Builder. It generates the code for instance to @ltera FPGAs.

Is it a commercial software? How good is it for modulator/demodulator designs?

Also, the books listed above: VHDL synthesis by KC Chang and Digital signal process w/ FPGA by Mayer, do they have any code examples, tips and advices on modulators designs, particularly in VHDL.

Thanks

 

[jay_ec_engg]

Ya KC Chang has code of FIR with very simple to some complex design... clock tree and synthesis is also added with the FIR design.. I think its good book for FIR...

 

[neocool]

What about using Digital Filter Analyzer (DFA) from digitalfilter.com? It can generate VHDL for simulated filter design. Coefficients are stored in a ROM table and intermediate multiplication results are stored in RAM block.. then summed.

I had a question for anyone who had used it before. How is it compared to Matlab R14 filter design toolbox mentioned above? I might have access to it as well.

I've studied the code generated by DFA. It's pretty good and understandable. However, when I've tried to map it for Spartan 2 (Target Device : x2s200 Target Package : pq208), it gave me the following errors:
Number of 4 input LUTs: 4,995 out of 4,704 106% (OVERMAPPED)
Number of occupied Slices: 2,675 out of 2,352 113% (OVERMAPPED)

Do filters really take so much space? Should I somehow simplify the code or use another device like Virtex with larger gate count? I suspect that ROM size in the design is unnecessary large (stores 16 coefficients taking 16/400 spaces). Also, maybe I could do something with multipliers, maybe use distributed arithmetic instead of using '*' function of IEEE.STD_LOGIC_ARITH.ALL library.

Does Matlab generates more compact design?


Thanks a lot in advance

 

[Jackwang]

I am designing a fir filter using FPGA.
I have completed vhdl code,but it doesn't work when I programmed it into device.
anyone can give a advice about hardware design by FPGA?

 

[Bob_C]

ONEoverT will give you a very efficient filter...code is readable and understandable. I've bought it and think it is great software. Unfortunately, it only runs on Windoze...no Linux version

Robert