H.Khan
Newbie level 1
I have an HDL Block in which the output follows the input in such a way that when input signal is binary 0, output remains 0 but when input turns 1, output turns 1 for a preset number of clock cycles (signal_length). i.e. input may remain high for suppose 65 or 66 clock cycles but output should remain high for preset number of clock cycles. I tried to accomplish the task with Verilog. But I am having an error and I don’t know how to rectify. Hope someone can help.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 module last_ind #( parameter MAX_LENGTH = 262144, parameter signal_length ) ( input clk, input [17:0] pkt_length, input tdata, output tlast ); reg [17:0] cnt = 0; always @ (posedge clk) begin if ((tdata==1) && (cnt<signal_length)) tlast <= 1; else cnt <= 0; end assign cnt <= cnt + 1'b1; endmodule
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