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how to define the clock frequency when synthesis and sta

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chico

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how to define the clock frequency when synthesis and sta, 120% max work frequency? Why? thanks!
 

hi
in general clock frequency is setup by the user defined as you wish to operate.. if you give start you design as 120%of operating frequency... it will optimize and worst case must be viewed such that slack is met. if you have negative slack then you can reduce you frequency incremental way check the tool can optimize the value.. but if negative slacks exits at operating frequency then no way you have to reduce the clock or restructure rtl by knowing the critical path ..in report timing summary..

It by experience if you set the clock as 120% you can finally achieve your operating frequency . it all worst case thats matter...

Regards
Shankar
 

i think the over-constrain should be 10 percent!!
 

check whether ur library includes the compensation for timings after SCAN insertion. If it is there, then use 10% (many follow this) over constraining CLOCK.
If ur library does not a/c for frequency drop after scan insertion, then 20% is required as margin.
 

In STA Usually we take double that of the maximum frequency
 

In STA Usually we take double that of the maximum frequency

Why should I define a double frequency for the STA checks? Could you explain please?
 

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