pbernardi
Full Member level 3
Hello,
In Verilog, I would like to declare some initial parameters which influence the number of parameters to be defined later into the code. For example:
So, if I change the NUMBER_OF_A, NUMBER_OF_B or NUMBER_OF_C, I would have different parameters defined on next lines. I tried to use some mix between parameter, vectors and generate without success. Any ideas?
In Verilog, I would like to declare some initial parameters which influence the number of parameters to be defined later into the code. For example:
Code:
parameter NUMBER_OF_A = 1;
parameter NUMBER_OF_B = 3;
parameter NUMBER_OF_C = 2;
(...)
parameter A1 = 8'd0;
parameter B1 = 8'd1;
parameter B2 = 8'd2;
parameter B3 = 8'd3;
parameter C1 = 8'd4;
parameter C2 = 8'd5;
So, if I change the NUMBER_OF_A, NUMBER_OF_B or NUMBER_OF_C, I would have different parameters defined on next lines. I tried to use some mix between parameter, vectors and generate without success. Any ideas?