How to create UCF, when using DCM?

[anee_anil]

Hi all,



I am doing my design using DCM through coregen, How to create Ucf for that?



my design entity

entity fiber_splitter is
port(clk_fpga : in std_logic;
pci_clk : in std_logic;
addr_bus : in std_logic_vector(7 downto 0);
data_i : in std_logic_vector(15 downto 0);
ipp : in std_logic;
write_read_en : in std_logic;
reset : in std_logic;
pulse_1usec_outp : out std_logic_vector(48 downto 0)
);
end fiber_splitter;



entity of DCM

entity dcm_fiber is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end dcm_fiber;



my clk_fpga runs at 10 Mh, I converted That to 100Mhz using DCM.

How to link those two clocks?

Please anybody create a ucf for this issue?

 

[devas]

Hi,

Create a timing constraint of 10MHz for your input clock signal. When you configured your DCM correctly, Xilinx knowns that the internal clock should run at 100MHz.

Devas